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With the dramatic increase in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware.
Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design.
Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers.
Table of Contents
Part I: The Origins of Congestion
An Introduction to Routing Congestion
Part II: The Estimation of Congestion
Placement-level Metrics for Routing Congestion
Synthesis-level Metrics for Routing Congestion
Part III: The Optimization of Congestion
Congestion Optimization During Interconnect Synthesis and Routing
Congestion Optimization During Placement
Congestion Optimization During Technology Mapping and Logic Synthesis
Congestion Implications of High Level Design
ISBN - 9788184893885
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Pages : 262
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